Input buffers often use a CMOS inverter optimized for TTL input levels. A nominal supply voltage is used at the input stage of the input buffer. As a result, the trip points strongly depend on the supply voltage, which causes increased propagation delays at low and high supply voltages. The current consumed by the previous approach, when operating at high supply voltages and high input levels, is higher than desirable for modern integrated circuit (IC) applications.
Input buffers are often designed to accommodate both TTL and CMOS input levels and to switch as fast as possible for a wide range of input rise/fall times. The input stage of such input buffers has a CMOS inverter with the PMOS pull up transistor of the inverter operating in the linear-saturated region throughout the standard TTL (i.e., 0-3 volt) input range. As the input supply voltage Vcc increases, the pull up current also increases, which results in a shift up of the trip point and consequently of the switching input level. As a result, longer propagation delays on the input rising edge and shorter propagation delay on the trailing edge are seen as the input supply voltage Vcc increases. Since the longest of these delays is taken as overall propagation delay, the result is a speed drop at both low and high input supply voltages Vcc.